Exam Ground Rule

• In class and 50 minutes
• 1 3x5 card
• Single purpose calculator - no cell phone apps
• Paper exam, bring a writing utensil

Exam Content

• Given a gate level schematic produce VHDL CSA using AND, OR, NOT, XOR
• Give a truth table produce VHDL using when/else statement
• Define and assign signals of type STD_LOGIC and STD_LOGIC_VECTOR
• Concatenate and subvectors for STD_LOGIC_VECTOR
• VHDL syntax needed to define an entity and architecture
• VHDL syntax to instantiate components
• Understand I/O and behavior of common basic building blocks. Entity declarations WILL be given to you on the exam.
  • genericAdder
  • genericMux
  • genericComparator
  • genericRegister
  • D flip flop
• Interpert a given process and determine its timing diagram
• Interpret a testbench and determine its timing diagram
• Interpret and produce code for a package file, constants and component declarations
• Understand, construct and produce timing diagram for enhancedPwm component
• Understand hazards and how D flip flops alleviate them
• Understand FPGA fabric, standard cell and its DFF and RAM
• VGA signaling, HSYNCH, HACTIVE, VSYNCH, VACTIVE
• Understand, construct and produce timing for videoSignalGenerator and scopeFace
• Datapath and control architecture and timing
• stopWatch control unit timing, wait states and VHDL code
• stopWatch datapath, define control word and complete control word table