| L1 |
Symbolic to VHDL, entity architecture, std_logic, signals |
HW #1 |
| L2 |
TT to VHDL, Literals, Vectors, Don't cares |
HW #2 |
| L3 |
Generics, Basic Building Block, Entity and Architecture |
HW #3 |
| L4 |
Sequential Building Blocks |
HW #4 |
| L5 |
Libraries, Testbench |
|
| L6 |
Design of enhanced PWM for lab 1 |
|
| Labor Day |
| 7 |
Lab 1 - Enhanced PWM |
| 8 |
Lab 1 - Enhanced PWM |
| L9 |
VHDL Synthesis - Porting PWM to PL in Zynq |
|
| L10 |
VGA Standard |
HW #7 |
| L11 |
Design of VGA to HDMI for lab 02 |
|
| 12 |
Lab 2 - VGA to HDMI |
| 13 |
Lab 2 - VGA to HDMI |
| 14 |
Lab 2 - VGA to HDMI |
| L15 |
Datapath and control architecture and timing |
|
| L16 |
Stopwatch Control Unit in VHDL |
|
| L17 |
Stopwatch Datapath in VHDL |
|
| L18 |
Exam Review |
|
| L19 |
Exam |
| L20 |
AD7606 chip, Input, Output and Behavior |
|
| L21 |
Design of datapath and control for Lab 3 |
|
| L22 |
Design of datapath and control for Lab 3 |
|
| 23 |
Lab 3 - Acquire |
| 24 |
Lab 3 - Acquire |
| 25 |
Lab 3 - Acquire |
| L26 |
BRAM, IP I/O and Behavior |
|
| L27 |
Design of datapath and control for Lab 4 |
|
| L28 |
Design of datapath and control for Lab 4 |
|
| 29 |
Lab 4 - acquireToDisplay |
| 30 |
Lab 4 - acquireToDisplay |
| 31 |
Lab 4 - acquireToDisplay |
| L32 |
Building Custom IP |
|
| L33 |
Programming Custom IP |
|
| 34 |
Lab 5 - enhancedPWM with Zynq |
| 35 |
Lab 5 - enhancedPWM with Zynq |
| 36 |
Lab 5 - enhancedPWM with Zynq |
| L37 |
Design of acquireToHdmi with Zynq for Lab 6 |
|
| 38 |
Lab 6 - acquireToHdmi with Zynq |
| 39 |
Lab 6 - acquireToHdmi with Zynq |
| 40 |
Lab 6 - acquireToHdmi with Zynq |
| 41 |
Lab 6 - acquireToHdmi with Zynq |