Homework #3

1. Draw a hardware schematic for the following circuits, similar to that shown on page 88 of my textbook linked on the main page. Use comparators, muxes and adders and do not show their internal organization. Whenever possible reduce the number of devices required to realize the design. You should assume that X, Y, and Z are 8-bit std_logic_vectors.
   1. if (X==0) then Z = X else Z = Y
   2. if (X==Y) then Z = Y else Z = X+Y
   3. if (X < Y) then Z = X+4 else Z = Y+6
   4. if (X > Y) then Z = X+5 else Z = X+6
2. Write a VHDL architecture for each if/then statement in the previous problem. Do each separately.