Homework #2

1. Understand all the examples from the associated lecture note.
2. Design a digital system with four bits of inputs I3 I2 I1 I0 and two bits of outputs O1 O0. At least one of the inputs is always equal to 1. The output encodes the index of the most significant 1 in the input. For example, if I3 I2 I1 I0 = 0101, then the index of the most significant 1 is 2, hence O1 O0 = 10. Hint, one of the inputs is a don't care, for that input, output the value 11.
   1. Complete truth table.
   2. Create the VHDL code for the circuit using behavioral model, that is using a when/else statement. You should use std_logic_vector for both the input and output.
3. Write the when/else statement for a 5-input majority circuit. The output from the circuit should equal 1 when a majority of the 5 inputs are logic 1. Use std_logic_vector for the input. Use don't cares on the input vectors to reduce the number of rows in the when/else statement. What is the minimum number of rows that will correctly generate the output?