Homework #1

• Come prepared to answer the following questions at the start of class.

1. Write out the entity and architecture code in VHDL for the following component. Make the components name "hw01-1".
   1. Try writing the code using signals for every wire that begins and ends inside the box. This will generate a lot of signals and many CSA's.
   2. Try writing one massive line of code for the entire architecture. So one CSA.
      
      
      
   3. Write out the entity and architecture code in VHDL for the following component. Make the components name "hw01-2". Be careful, you should not call the output of the red AND gate "X" because this output needs to be the input of the orange AND gate. So instead, make the red AND gate output a signal in one CSA and then assign X this signals value in a seperate CSA.